1. Field of the Invention
This invention relates to processes for preparing Josephson junction integrated circuits, and more particularly to a process for sealing pinholes, in a composite insulating/spacing etch-stop layer on a metal groundplane, which are opened during metallization pattern etching.
2. Description of Related Art
Typical Josephson junction integrated circuit devices include a niobium groundplane insulated with a composite insulating/spacing etch-stop layer of niobium pentoxide/silicon monoxide. The silicon monoxide operates as a dielectric layer, which provides spacing required to achieve the desired transmission line qualities, and also has very desirable etch-stop qualities. The low dielectric constant and the etch resistance of the silicon monoxide make it ideal for the purpose. Silicon monoxide deposition processes, however, are such that it is difficult to deposit a gap-free continuous layer of silicon monoxide sufficiently thin for the purpose. The layer must be thin to exhibit the desired dielectric and spacing characteristics necessary for transmission lines to carry the fast risetime superconducting signals inherent in Josephson technology. A layer of niobium pentoxide, relatively easy to grow and relatively defect-free, is commonly included under the silicon monoxide. Niobium pentoxide is not used alone (without the silicon monoxide) since it is not adequate as an etch-stop. The dual niobium pentoxide/silicon monoxide composite insulating/spacing etch-stop layer is continuous and relatively defect-free. The silicon monoxide component of the composite layer, however, suffers from the drawback that during deposition it leaves deposits on the internal surfaces of the process chamber. These deposits may flake off in minute flakes, some of which are deposited as contaminants on the wafer. Such contaminants create mechanically unstable sites for later development of pinholes. Since the sites may be microscopic flakes of the process material silicon monoxide (as well as of external contaminants), such sites are difficult to identify in the silicon monoxide etch/stop layer. Such sites are virtually impossible to repair.
Processes for developing integrated circuits over the wafer, by a sequence of metallization deposition, masking, metallization pattern etching, oxidation, etc. have been reported. In such processes, the wafer after metallization may be subjected to the corrosive environment required by subtractive etching. The etchants required are so powerful that processing, particularly the metallization patterning etch step, may create pinholes through the composite insulating/spacing etch-stop layer at susceptible sites under certain conditions, exposing the groundplane metal.
Pinhole sites, resulting from random distributions of contaminant particles and microscopic gaps in silicon monoxide coverage, occur with a statistical probability and with a statistically variable (and thus unknown) placement over the wafer.
Integrated circuit devices based on Josephson edge junctions, where very tiny Josephson junctions are placed on the edges of metallization interconnections, are particularly susceptible to faults caused by pinhole defects, because of the very thin layers required by the technology. There are no easy methods known to test for pinhole sites. The requirements of Josephson junction technology make it difficult to make the groundplane insulating/spacing etch-stop layer more robust. The layer must be thin and have the correct net dielectric constant to achieve the necessary transmission line characteristics. Dimensional requirements in the required superconductive materials (including niobium, lead and alloys such as lead-gold-indium) limit the technologies that may be used for subtractive etching. Pinholes which can expose a groundplane metal can occur. Josephson junction circuits are not generally capable of proper operation in the case of pinhole faults which might cause unwanted conductive paths. There are no easy methods known for determining the exact location of pinholes.
3. Related Prior Art Patents
U.S. Pat. No. 3,436,258 et al, METHOD OF FORMING AN INSULATED GROUND PLANE FOR A CRYOGENIC DEVICE, granted Apr. 1, 1969, shows a method of forming an insulated groundplane for a cryogenic device, which method includes the preparation of an oxide insulating layer by anodizing the film. Neugebauer et al solves the resulting pinhole problem by providing a smooth substrate and a high purity, superconductive metallic film upon which the metal oxide insulator is formed. Neugebauer et al does not, however, perform a reanodization function.
U.S. Pat. No. 3,784,452, Martens et al, METHOD OF TREATING THE SURFACE OF SUPERCONDUCTING NIOBIUM CAVITY RESONATORS, granted Jan. 8, 1974. Martens et al shows a two-step process for providing a niobium oxide layer on a niobium surface by first preoxidizing the niobium surface, chemically removing the resultant niobium oxide layer, and thereafter producing a niobium oxide layer at the niobium surface, through a renewed anodic oxidation. Martens et al does not suggest reanodization subsequent to layer growth as provided by this patent specification.
U.S. Pat. No. 3,806,430, Laibowitz et al, METHOD FOR FABRICATING ANODIC FILMS, granted Apr. 23, 1974. Laibowitz et al shows a process for chemically smoothing a metal layer by multiple anodizing and etching steps to eliminate defects such as cavities and hillocks.
U.S. Pat. No. 3,902,975, Martens, METHOD FOR TREATING NIOBIUM SURFACES USED IN AC CIRCUIT APPLICATIONS, granted Sept. 2, 1975. Martens shows a method for treating niobium surfaces by first producing an anodized niobium pentoxide layer and then removing the niobium pentoxide layer to result in a finished oxide-free product.
4. Related Prior Art Publications
Broom et al, ISOLATION TECHNIQUE FOR JOSEPHSON JUNCTION GATES, IBM Technical Disclosure Bulletin, Volume 18, Number 5, October 1975, page 1558. Broom et al shows a technique for first anodizing a niobium groundplane, then depositing a layer of silicon oxide over the niobium pentoxide layer thus formed, and finally, by treating with an RF plasma treatment to remove some silicon oxide by the oxygen plasma, convert it to silicon dioxide, and by scattering redeposit it everywhere, to cover any pinholes or previously shadowed edges. Broom et al recommends the use of silicon dioxide to seal ". . . any exposed metal surfaces at the pinholes or edges previously shadowed . . . " This is a different technique, applied at a different stage in the process (after silicon monoxide deposition) from the application of this technique (after metallization patterning etch) and does not seal pinholes opened during the metallization patterning etch step.